In integrated circuit fabrication, the reduction of memory cell capacitance due to a decrease in the area of a memory cell may hinder higher integration of dynamic random access memories (DRAMs). Furthermore, a reduction in memory cell capacitance may lower the readout capability, increase the soft error rate, and make low voltage operation difficult. Thus, it would be desirable to reduce the size of the memory cell in order to achieve the high integration of integrated circuit devices without significantly decreasing the memory cell capacitance.
It is known that the charge Q stored in a capacitor is determined by multiplying the capacitance C of the capacitor by the capacitor's operating voltage V. This relationship can be expressed by the equation Q=C*V. The capacitance C of a capacitor can be expressed as C=A.epsilon..sub.o .epsilon..sub.r /D, where A is the effective area of the capacitor, .epsilon..sub.o is the dielectric constant of the capacitor's dielectric in a vacuum state, .epsilon..sub.r is the relative dielectric constant of the capacitor's dielectric, and D is the thickness of the capacitor's dielectric. Thus, the capacitance C of the capacitor can be increased by increasing the effective area A of the capacitor, increasing the dielectric constant .epsilon..sub.r of the dielectric, and/or decreasing the thickness D of the dielectric.
As a result, lower electrodes having a three-dimensional structure have been proposed to increase the effective area of the capacitor. Examples of three-dimensional lower electrode structures include a fin-shaped lower electrode, a box structure lower electrode and a cylindrical-shaped lower electrode. Of particular significance is the cylindrical lower electrode which is widely used because the inner surface and the outer surface of the cylinder portion of the electrode can be used to increase effective surface area.
FIGS. 1 to 5 are cross-sectional views illustrating steps of a conventional method for fabricating a capacitor having a cylindrical lower electrode. FIG. 1 shows the steps of forming an insulating layer 20 and a conductive layer 30. As shown, a first insulating layer 20 of borophosphosilicate glass (BPSG) is formed to a thickness of about 2000 .ANG. on a semiconductor substrate 10. The first insulating layer 20 is then patterned to form a contact hole that exposes a predetermined area of the semiconductor substrate 10. The conductive layer 30 is formed on the insulating layer 20 to a thickness of about 7000 .ANG., thereby filling the contact hole. The conductive layer can be a layer of polysilicon.
FIG. 2 shows the steps of forming a photoresist pattern 40 and a spacer 50. Specifically, a photoresist layer is formed on the conductive layer 30 and is patterned to expose the conductive layer 30, thereby forming the photoresist pattern 40 on the conductive layer 30 opposite the contact hole. Because the conductive layer 30 is exposed when the photoresist layer is patterned, the photoresist layer should be overexposed.
When the photoresist layer is overexposed to form the photoresist pattern 40, however, a smaller pattern than desired may be formed. With reference to FIG. 2, the photoresist pattern 40 may have a width narrower than that of the desired pattern. Because the portion of the conductive layer 30 where the photoresist pattern 40 is formed is the area defining the inner surface of the lower electrode, as the width of the photoresist pattern 40 narrows due to the overexposure, the inner diameter of the lower electrode may likewise decrease. The effective surface area of the electrode may thus decrease, and therefore, the capacitance of the capacitor may be reduced.
Next, a second insulating layer of a silicon oxide is formed on the photoresist pattern 40 and the conductive layer 30. The second insulating layer is preferably formed at a relatively low temperature between 300 and 450.degree. C. so that the photoresist pattern 40 is not significantly damaged. The second insulating layer is then anisotropically etched to form the spacer 50 on the sidewall of the photoresist pattern 40, as shown in FIG. 2.
FIG. 3 shows the step of forming a modified conductive layer 30a. In particular, using the photoresist pattern 40 and the spacer 50 as etching masks, the conductive layer 30 is etched to a predetermined thickness that does not expose the insulating layer pattern 20. Thus, the modified conductive layer 30a is formed, as shown in FIG. 3.
FIG. 4 shows the steps of forming a modified spacer 50a and a lower electrode 30b. First, the photoresist pattern 40 is removed through an ashing process. Residues generated by the ashing process can be removed using an etching solution, such as a sulfuric acid solution. This process may also partially remove the spacer 50 so that the size of the spacer 50 is diminished, thereby forming the modified spacer 50a. The modified conductive layer 30a is then etched using the modified spacer 50a as an etching mask to expose the insulating layer pattern 20 at the outer edge of the modified spacer 50a, thereby forming the cylindrical lower electrode 30b.
As described above, the width of the spacer 50 may be reduced when the photoresist pattern 40 is removed. Therefore, an upper portion A of the sidewall of the lower electrode 30b may also be etched so that a step may be formed in the sidewall of the lower electrode 30b. This may result in a pattern failure in the lower electrode 30b.
FIG. 5 shows the steps of forming a modified insulating layer 20a, a dielectric layer 60, and an upper electrode 70. First, the modified spacer 50a is removed using a buffered oxide etchant (BOE). A portion of the insulating layer pattern 20 is also removed with the modified spacer 50a so as to expose a bottom portion of the lower electrode 30b, thereby forming the modified insulating layer 20a.
The dielectric layer 60 is then deposited to a thickness of about 50 .ANG. on the lower electrode 30b and the modified insulating layer 20a. The dielectric layer 60, however, may be improperly formed on the lower electrode 30b because of the step at the upper portion A of the sidewall. The upper electrode 70 is then formed on the dielectric layer 60, thereby completing a cylindrical capacitor. The upper electrode can be a layer of polysilicon.
According to a conventional method described above for fabricating cylindrical capacitor, the photoresist pattern 40 may be narrower in width than desired if the photoresist layer is overexposed when forming the photoresist pattern 40. By narrowing the width of the photoresist pattern 40, the effective area of the capacitor may be reduced, thus reducing the capacitance of the capacitor. Moreover, an undesirable pattern failure may occur in the lower electrode 30b when the photoresist pattern 40 is removed because the spacer 50 is also partially removed.